1. Field of the Invention
This invention relates to a method of fabricating a high-integration, high-speed semiconductor device.
2. Description of the Prior Art
As the packing density of semiconductor integrated circuit devices increases, the size of circuit elements such as MOS transistors reduces. In such devices, the depth of the source/drain p-n junction also must be reduced if proper transistor operation is to be guaranteed. This requirement, however, involves an increase in the parasitic source/drain resistance, and is hence contradictory to the fabrication of MOS transistors with higher operating speeds.
Among methods to solve the above problem, recent attention has been directed to a technique (silicided junction method) whereby a low-resistance, refractory metal silicide layer is formed on a highly doped diffusion layer of a silicon substrate in self-alignment with an exposed region of the silicon substrate. In this method, ion implantation is often used to introduce dopants (impurities for generating electric carriers). When the introduction of dopants is viewed in terms of time relationship to the formation of the silicide layer, a method wherein the dopant implantation is performed after the formation of the silicide layer is proposed, for example, in the 1986 Symposium on VLSI Technology, Digest of Technical Papers (1986), pp. 49-50.
According to the proposed method, ion implantation is carried out in such a manner that most of the total dose comes to rest within the titanium silicide thin film, and a shallow junction is formed by subsequent drive-in (activation) heat treatment. Therefore, this method can serve to minimize the damage done to the silicon substrate by ion implantation, and is said to be very effective in forming shallow p-n junctions.
However, with the above method, the dopant (boron or arsenic) implanted into the titanium silicide layer may become reacted with the constituent metal element (titanium in the case of titanium silicide) in the silicide during the drive-in heat treatment, forming a compound (TiB.sub.2 or TiAs) with the dopant, and thus significantly reducing the implanted dose that can be electrically activated in the silicon substrate.
This situation is illustrated in FIG. 4 taking, as an example, a p.sup.+ -n junction formed by boron implantation. The figure also shows a characteristic curve for the depth versus the boron density of the ion implantation. Under this ion implantation condition, most of the boron (more than 80% of the total implant dose) rests within a titanium silicide layer 5. These boron atoms react with the constituent metal element (titanium) in the titanium silicide to form titanium boride 13 (e.g., TiB.sub.2) which is deposited at the titanium silicide/silicon substrate interface. This results in a significant reduction in the amount of boron that can be electrically activated in the silicon substrate 1. Consequently, the density of carriers 14 (holes) existing at the surface region of the n-type silicon substrate 1 is reduced to less than 20% of the total implant dose. The resulting problem is an crease in the contact resistance at the titanium silicide/silicon substrate interface or the inability to form ohmic contacts. In the figure, the reference numeral 15 indicates the p.sup.+ -n junction.
The above problem is reported, for example, in Applied Physics Letters 52 (1988), pp. 1803-1805.